The following disclosure relates to semiconductor devices.
In integrated circuit design there are many applications that include high performance, on-chip capacitors. These applications include, for example, voltage control oscillators, phase-lock loops, operational amplifiers, and switching capacitors. On-chip capacitors can be used, e.g., to isolate digital and analog integrated circuits from noise created within an integrated circuit system or to store charge within an integrated circuit system.
Conventional on-chip capacitors can be configured as Metal-Oxide-Metal capacitors (MOMs). Referring to FIG. 1, the construction of a conventional MOM capacitor 100 is illustrated. MOM capacitor 100 includes two nodes 102 and 104 that are formed on conductor layers 106 and 108, respectively. A substrate 110 forms a base for MOM capacitor 100. Conductor layers 106 and 108 are separated by a dielectric 112 (e.g., silicon dioxide). Substrate 110 and conductor layer 108 can also be separated by a dielectric (not shown). In addition to a device (parallel plate) capacitance (Cpp) that is formed between nodes 102 and 104, an undesirable parasitic capacitance (Cs) may also be formed between substrate 110 and node 104 in a conventional MOM structure.
In general, in one aspect, this specification describes a capacitor structure. The capacitor structure includes a substrate, a first group of conducting strips, a second group of conducting strips, a third group of conducting strips, and a fourth group of conducting strips.
The first group of conducting strips are arranged substantially parallel to each other within a first layer disposed on the substrate. The first group of conducting strips are also connected to a first node and are in electrical communication with each other. The second group of conducting strips are arranged substantially parallel to each other and alternate with the first group of conducting strips within the first layer. The second group of conducting strips are connected to a second node and are in electrical communication with each other. The third group of conducting strips are arranged substantially parallel to each other within a second layer that at least partially overlies the first layer. The third group of conducting strips are in electrical communication with each other and with the first group of conducting strips. The third group of conducting strips are further substantially perpendicular to the first group of conducting strips and the second group of conducting strips. The fourth group of conducting strips are arranged substantially parallel to each other and alternate with the third group of conducting strips within the second layer. The fourth group of conducting strips are in electrical communication with each other and with the second group of conducting strips. The fourth group of conducting strips are further substantially perpendicular to the first group of conducting strips and the second group of conducting strips.
Particular implementations can include one or more of the following. The capacitor structure can further include a dielectric interposed between the first and second layers. The dielectric can be a layer of silicon dioxide. The capacitor structure can further include a guardband spaced from the first and second nodes. The guardband can be comprised of a conductive material—e.g., aluminum, polysilicon, or copper. The guardband can be spaced approximately a predetermined distance (dg) from the first and second nodes, in which adjacent conducting strips of the first and second layers are spaced apart approximately a predetermined distance (dh), and the distance (dg) is selected to be substantially twice the distance (dh). The guardband can be located on a single layer or distributed over multiple layers. The guardband can encircle the first and second layers of conducting strips. At least one of the first, second, third and fourth groups of conducting strips can be connected by a corresponding base strip. The first group of conducting strips can be connected to the third group of conducting strips by vertical vias. The second group of conducting strips can be connected to the fourth group of conducting strips by vertical vias. The second layer can substantially overlie the first layer.
In general, in another aspect, this specification describes a capacitor structure that includes a substrate, a first group of conducting strips, a second group of conducting strips, a third group of conducting strips, a fourth group of conducting strips, a first set of vertical vias, a second set of vertical vias, a third set of vertical vias, and a fourth set of vertical vias.
The first group of conducting strips are arranged substantially parallel to each other within a first layer disposed on the substrate. The first group of conducting strips are connected to a first node and are connected to a first base strip. The second group of conducting strips are arranged substantially parallel to each other and alternate with the first group of conducting strips within the first layer. The second group of conducting strips are connected to a second node and are connected to a second base strip. The third group of conducting strips are arranged substantially parallel to each other within a second layer that at least partially overlies the first layer. The third group of conducting strips are connected to the first node and are connected to a third base strip. The third group of conducting strips are substantially parallel to and substantially overlie the first group of conducting strips. The fourth group of conducting strips are arranged substantially parallel to each other and alternate with the third group of conducting strips within the second layer. The fourth group of conducting strips are connected to the second node and are connected to a fourth base strip. The fourth group of conducting strips are also substantially parallel to and substantially overlie the second group of conducting strips. The first set of vertical vias interconnect the first group of conducting strips to the third group of conducting strips. The second set of vertical vias interconnect the second group of conducting strips to the fourth group of conducting strips. The third set of vertical vias interconnect the first base strip to the third base strip. The fourth set of vertical vias interconnect the second base strip to the fourth base strip.
Particular implementations can include one or more of the following. The third set and fourth set of vertical vias can be each placed at locations along a respective base strip substantially adjacent to vertical vias of an opposite node that are located on one or more of the first, second, third or fourth groups of conducting strips.
Implementations can include one or more of the following advantages. On-chip capacitance structures are provided that are highly immune to noise fluctuations that may be present on a substrate. In addition, the on-chip capacitance structures provide a high capacitance-per-volume. In one implementation, vertical vias are used within a base strip to form base strip via capacitances that further increase the overall capacitance-per-volume of the capacitance structure. On-chip capacitance structures are provided that also have an efficient use of space.
The details of one or more implementations are set forth in the accompanying drawings and the description below. Other features and advantages will be apparent from the description and drawings, and from the claims.
Like reference symbols in the various drawings indicate like elements.